Spacer etching poses a challenge for fabricating FinFET devices. In particular, the fin spacer must be completely removed. Failure to remove the spacer can induce embedded silicon germanium (eSiGe) defects, and can also introduce electrical performance degradation. Removing the spacer with a large nitride etch can cause significant nitride cap loss, which can lead to an overlap nitride bump or potential excessive gate spacer thinning. A high overlap nitride bump can give rise to a large burden for the downstream poly open process, and gate spacer thinning may lead to unwanted epitaxial growth during the eSiGe or embedded silicon phosphide (eSiP) processes.
A known approach for FinFET spacer etching involves four steps: 1) spacer deposition; 2) spacer main etch (ME); 3) spacer over etch (OE); and 4) silicon (Si) recess, as illustrated in FIGS. 1A through 1D, respectively. During the spacer deposition step (FIG. 1A), a gate 101 is first formed on a substrate 103 having a silicon fin, the gate 101 having a nitride cap 105 on an upper surface thereof and an oxide cap 107 on an upper surface of the nitride cap 105. In particular, the silicon fin may be part of the substrate 101 or it may be formed distinct from the substrate 101. Thereafter, a dielectric layer 109, e.g., silicon nitride (Si3N4), silicon dioxide (SiO2), ceramic coating (SiOCN), boroncarbonitride (SiBCN), or any common dielectric material used in the semiconductor industry, is formed over the silicon fin of the substrate 103 and the gate 101. Next, as illustrated in FIG. 1B, during the spacer ME step, the dielectric layer 109 is removed from all horizontal surfaces, e.g., the upper surface of the oxide cap 107, an upper surface of the silicon fin of the substrate 103, and the substrate 103. During the spacer OE step (FIG. 1C), portions of the dielectric layer 109 from the side surfaces of the gate 101 and the silicon fin of the substrate 103 are removed along with the oxide cap 107. In addition, portions of the nitride cap 105 and portions of the silicon fin of the substrate 103 are also removed. Last, during the Si recess step, additional portions of the dielectric layer 109 are removed from the side surfaces of the silicon fin of the substrate 103 along with the remaining portion of the silicon fin, as shown in FIG. 1D. A portion of the substrate 105 below the silicon fin 101 is also recessed. However, some of the dielectric layer 109 remains adjacent to the recess in the substrate 103. Further processing to remove the remaining dielectric layer 109 would also remove part of the nitride cap 105 and/or would thin the gate spacers.
A need therefore exists for methodology removing the whole dielectric spacer from the side surfaces of the fin faster than after recessing the fin and without large nitride cap loss, and the resulting device.